1. Field of the Invention
The present invention relates to a multiport frame exchange system having a plurality of input lines and a plurality of output lines wherein frame data inputted from the plurality of input lines are outputted to desired output lines based on the header information of the frames.
2. Description of the Related Art
With the growing number of client/server systems configured for in-house networks and LANs and with the increasing volume of data handled by these systems including audio information, still pictures, and moving pictures, increasing attention has been focused on the technology of structuring these networks. Frame exchange devices having a plurality of input and output ports have come into use for constructing these types of networks. The frames dealt with include MAC (Media Access Control) frames handled on the MAC layer or IP (Internet Protocol) packets handled on the network layer.
In such devices, header processing is executed within, for example, a CPU, and takes on a construction such as shown in FIG. 1. In this construction, frames inputted to line interface unit 900 are sent to memory 930 of header processor 910, and following execution of address processing at CPU 920, are sent to line interface unit 901, which is connected to the line of the output destination. Data transfer at this time is carried out using a common bus, and moreover, access of memory 930 during processing by CPU 920 is also achieved using this bus. As a consequence, use of this bus by a particular line interface unit prevents use by another line interface unit or by CPU 920, thereby interfering with application to high-speed lines or the accommodation of a large number of lines.
As one data transfer system directed toward improving this situation, Japanese Patent Laid-open No. 108242/92 proposes the structure shown in FIG. 2. In this system, header information including, for example, the frame destination, is stored in local memory 1020 of header processor 1010 while the data section of the frame is stored in main memory 1040; and at the time of frame transmission, line interface units 1000 and 1001 operate by accessing data in main memory 1040 and accessing header information in local memory 1020 by way of bus transceivers 1050-1053. In this way, header processing can be performed without monopolizing the common bus, thereby increasing opportunities of data transmission and raising throughput. However, line interface units 1000 and 1001 both share use of the common bus for data transmission, and as a result, high-speed lines and accommodation of a large number of lines cannot be fully implemented.
In the above-described systems of the prior art, data transmission is effected over a common bus, and as a consequence, full implementation of high-speed lines and the accommodation of multiple lines is compromised.